This invention relates in general to the treatment of various structures made from semiconductor materials for applications in microelectronics, optics and optoelectronics. Generally, these structures are multilayer structures including a so-called “working” electrically conductive layer and an electrically insulating layer. The working layer usually is a superficial layer while the electrically insulating layer is buried in the thickness of the structure. Typical structures can for example include Silicon On Insulator (SOI) structures. In this case, the working layer is the superficial thin layer of silicon and the buried insulating layer is usually an oxide. Of course, the skilled artisan is aware of other SOI and multilayer structures that are commonly used in this art.
Methods for treating an electrically conductive working layer of a multilayer structure made from semiconductor materials of the type mentioned herein are already known. Such methods make it possible to constitute islands of electrically conductive material in the working layer of a structure (e.g., silicon in the case of an SOI). It is indeed necessary to constitute such islands in order to realize certain operations on the structures relating to the invention. These operations comprise in particular the characterization of the electrical properties of the structure. Such characterization can in particular be performed by implementing at least one pseudo-component of the structure, and this is generally referred to as pseudo-MOSFET.
The pseudo-MOSFET is a macroscopic device similar to a transistor, much which requires for its manufacture a very limited number of technological steps. Such a device can in particular be constituted in a structure such as that mentioned above. This device further presents the advantage of providing results that are characteristic of the material of the working layer in which it is manufactured, without requiring modifications that are inherent to the CMOS manufacturing method (channel layout, etc.). It is therefore simple to constitute in a structure (SOI or other) such a device, in order to characterize the electrical properties of this structure and in particular of its working layer.
A pseudo-MOSFET incorporated into an SOI uses the intrinsic MOS structure of the SOI, by using the buried oxide as a dielectric gate, the substrate as a gate, and two contacts on the working layer as source and drain. It has the form of a MOSFET, but inversed. It is based on a simple MOSFET using contacts of the Schottky type. Such a pseudo-MOSFET is shown schematically in FIG. 1 which illustrates the case of an SOI 10 comprising a thin working layer of silicon 11, an insulating layer 12 and a substrate layer 13. A pseudo-MOSFET was constituted in the SOI, in a determined region of the latter. This pseudo-MOSFET comprises two contacts S and D in the working layer 11, for the source and drain of the device respectively. Substrate layer 13 serves as a gate for it (contact Vs).
The pseudo-MOSFET thus constitutes an advantageous device for the characterization of semiconductor structures. It is manufactured by spatially defining a given pattern in the upper layer of this type of structure. This pattern is thus electrically isolated from the substrate layer 13 of the structure, thanks to the insulating layer 12. It can be implemented according to the so-called “T-MOS Test” method of characterization. The “v-MOS Test” method makes it possible to realize on the front side of the structure (i. e. the side that bears the working layer of the structure) two contacts via pressure of two tungsten carbide points. These two contacts—which correspond to contacts S and D in FIG. 1—are applied to the center of the pattern defined in the upper layer of the structure.
The structure thus constitutes a characterization sample (the terms “structure” and “sample” shall be used indifferently in the remainder of this text). The rear side of the structure rests on a conductor plate on which is applied voltage. This contact on the rear side of the structure corresponds to the gate contact.
Within the framework of the “T-MOS Test” method, several isolated islands are realized one after the other in the structure to be qualified, such as shown in FIG. 2. Each one of these islands 15 is separated from the other islands by trenches along which the material of the working superficial layer has been removed, in such a way that the insulating layer is flush in these trenches. And the characterization of the structure according to this method is in general accomplished by characterizing the various islands 15 of the structure, by applying the discreet contacts mentioned above.
It is thus possible to realize a mapping of the electrical properties of the structure, in its different islands. Note that the characterized electrical parameters are typically the following: ue (electron mobility), ph (hole mobility), Dit (interface state density), Vth (threshold voltage), VFB (flat band voltage), Qbox (charge of the insulating layer). This method of characterization thus makes it possible to perform in a synoptic manner a mapping characterizing different islands of a same structure, which is advantageous.
In order to manufacture islands such as those shown in FIG. 2, a lithography method is implemented. This type of method makes it possible to constitute several islands, even on structures of small size (with a diameter of 3 inches, for example). But such a procedure is cumbersome to implement, and costly. Furthermore, this type of method does not in general make it possible to constitute islands over the entire surface of a structure of significant size (e. g. case with diameters of 8 inches, or even more).
In a variant of the manufacture of islands by lithography, it is possible to manufacture on a sample structure an island of characterization by etching the structure selectively through a “hard” masking. In this variant, a selective attack of the structure by wet etching is generally implemented, in order to constitute the island.
FIG. 3 thus shows a sample structure 100 related to the invention. Two 0-rings 21a, 21b are each pressed against a respective glass plate 20a, 20b and one of the sides of the sample structure. This pressure is provided by means 22. The two 0-rings thus define across from the two sides of the sample structure 100 two regions 101a, 101b of the sample which are isolated in a sealed manner.
Sample 100 with its isolated regions is then exposed to an etching solution capable of selectively etching the working layer of the sample-for example KOH in the case of a silicon working layer sample. By “selectively” etching the working layer is meant that only the working layer is etched, and that the adjacent layers are not etched. This results in wet etching of the working layer, except across from regions 101a and 101b in which the layers of the original structure are preserved. These regions correspond to an island at the level of which the sample shall be able to be characterized in the same manner as disclosed above concerning the “T-MOS Test” method.
In this way, a sample is manufactured having a single island. And the manufacturing method for this island, which implements wet etching, is not exposed to the inconveniences mentioned above concerning the method of constituting islands by lithography. This type of method by wet etching is therefore advantageous. But this type of method however only makes it possible to constitute a single island on a sample structure. It therefore does not make it possible to constitute several islands on the surface of the structure, in order to realize a mapping such as that mentioned above. Thus, this prior art technique need improvement.